The present invention relates to integrated memory circuits such as dynamic random access memory integrated circuits (DRAM), static memory circuits, or the like. More particularly, the present invention relates to an improved dynamic random access memory architecture wherein the master data switches and the connections thereto are laid out such that space usage on the chip is substantially reduced.
Memory circuits such as dynamic random access memory (DRAM) circuits have long been employed in electronic equipment such as computers. In designing DRAM circuits, the challenge has been to maximize performance (in terms of delay, power consumption, density, and the like) while reducing the size of the integrated circuit to improve performance. There is provided in the art a DRAM architecture known as a stitched word line architecture wherein the word lines are formed by stitching together a low resistance conductor (typically formed of a metal such as aluminum or copper) to a gate conductor portion by the use of interdielectric contacts.
To facilitate discussion FIG. 1 illustrates a portion of a word line 100 including a low resistance conductor 102 and a gate conductor portion 104. Low resistance conductor 102, which is typically formed of a low resistance material such as aluminum or copper or one of their alloys, is disposed above and separated from gate conductor portion 104 by a dielectric layer. Gate conductor portion 104, which may be one continuous piece or may be segmented, represents the conductor that couples to the gate of the access transistors, i.e., the transistors that control the flow of current to and from the storage cells. To couple low resistance conductor 102 to gate conductor portion 104, a plurality of contacts, or stitches 106 are shown.
The use of a stitched word line architecture increases the speed at which the potential on the word line can be switched since speed is limited by the value of the RC product of the word line as a unit. Since the sheet resistance of the material forming low resistance conductor 102 is substantially lower than the sheet resistance of the material forming the gate conductor portion, the use of low resistance conductor 102 greatly reduces the resistance (R) at the expense of little additional capacitance (C). Thus, the value of the RC product is greatly reduced, enabling an increase the switching speed of the word line.
Although the use of the stitched word line architecture advantageously improves performance, there is required on the DRAM chip a stitch region for accommodating contacts 106. To further elaborate, FIG. 2 illustrates a portion of an exemplary DRAM circuit wherein the stitched word line architecture is employed. Referring now the FIG. 2, DRAM portion 200 includes arrays of memory cells 202, 204, 206, and 208. Within an array, word lines 210 are disposed horizontally (i.e., in the X direction) in general while bit line pairs 212 are disposed substantially orthogonal to the word lines, i.e., they are disposed vertically (i.e., in the Y direction) in general.
It should be understood that while the general direction of the word lines (as well as other horizontal running structures) is typically horizontal, local variations in the general direction may occur in some DRAMs. Likewise, although the general direction of the bit lines (as well as other vertical running structures) is typically vertical, local variations may also occur. In these cases, the local intersection between a word line and a bit line may not be exactly orthogonal, as may be expected, although the general direction of a word line and the general direction of a bit line may form one. Thus, the directions discussed herein should be understood in the general sense and are not intended to limit the inventions to absolute horizontal or vertical directions. It should also be understood that each of word lines 210 represents a stitched unit wherein a low resistance conductor is stitched to an underlying gate conductor portion in the manner discussed earlier. Although only some exemplary word lines and bit line pairs are shown in FIG. 2, it should also be understood that an array may have as many word lines and bit line pairs as needed.
The contacts (e.g., contacts 106 of FIG. 1) employed to stitch the low resistance conductor of a word line to its gate conductor portion are disposed in the stitch regions which are located adjacent to the arrays generally in the horizontal (or X) direction. With reference to FIG. 2, the contacts for stitching the low resistance conductor to the gate conductor portion of the word lines are located in stitch regions 214, and 216, which are disposed between adjacent columns of arrays.
The bit line pairs 212 of FIG. 2 are provided in pairs in accordance with the folded bit line architecture that is well known to those skilled in the art of DRAM design. Generally speaking, in the folded bit line architecture, two bit lines are employed to sense the charged stored in a memory cell of the DRAM. In preparation for reading the stored charge, both the true and complement bit lines are precharged to a predefined level. Since the word line is connected to the gate of the access transistor that controls the storage cell, raising the word line connects the storage cell to the true bit line. The stored charge will either increase or decrease the precharged potential already existing on true bit line.
An array sense amplifier coupling to both the true and compliment bit lines would then compare the potential of the true bit line to that of the compliment bit line (which is unconnected to the storage cell and therefore does not have its potential changed by the charge in the storage cell). The result of the comparison is then provided through additional circuitry (which will be described further in connection with FIG. 3 herein) to the pins of the DRAM circuit to enable an external circuit to ascertain the logic value stored in the storage cell.
With reference to FIG. 2, the array sense amplifiers are disposed in the array sense amplifier regions which are disposed above and below each array. In the example of FIG. 2, an interleaved sense amplifier architecture is employed wherein the sense amplifiers employed for sensing the potentials on adjacent bit line pairs are located at opposite ends of an array. By way of example, sense amplifier 220, which is employed to detect the potentials on bit line pair 212a, is disposed in sense amplifier region 222. Sense amplifier 224, which is employed to sense the potentials on adjacent bit line pair 212b, is disposed in sense amplifier region 226. As can be seen in FIG. 2, sense amplifier regions 222 and 226 are disposed at opposite ends of array 202. The interleaved sense amplifier architecture is well known in the art and will not be further elaborated here.
The use of an interleaved sense amplifier architecture advantageously increases the sense amplifier pitch relative to the bit line pitch, thereby providing more room in each sense amplifier region to implement the sense amplifiers. To reduce the number of sense amplifiers required per DRAM circuit, each sense amplifier is typically connected to the two bit line pairs of the two arrays adjacent to it and multiplexed between the two bit line pairs as needed. By way of example, sense amplifier 220 is coupled to both bit line pairs 212a and 212e, and is multiplexed between these two bit line pairs to enable sense amplifier 220 to service the sensing need of both of these bit line pairs. In this manner, the number of sense amplifiers required per DRAM circuit may be reduced by approximately half.
As mentioned in connection with FIG. 2, additional circuitry is typically required to output the logic state sensed by the array sense amplifiers (e.g., sense amplifiers 224 of FIG. 2) to the off-chip driver (which provides that sensed logic state to the pin of the DRAM IC to be read by the requesting external circuit). One implementation of the aforementioned additional circuitry is depicted in FIG. 3. Referring now to FIG. 3, there is shown a pair of bit lines which include a true bit line 302 and a compliment bit line 304. As mentioned earlier, an array sense amplifier may be employed to compare the potential on true bit line 302 with the potential on compliment bit line 304 to ascertained the charge stored in the memory cell accessed (which modifies the potential on true bit line 302). The result of the comparison is output by array sense amplifier 306 to local data lines 308 and 310. Local data line 308 represents the true data line and local data line 310 represents its compliment.
A pair of master data switches 312 and 314 couple to local data lines 308 and 310 to master data lines 316 and 318. As in the case of the local data lines, master data line 316 represents the true master data line while master data line 318 represents its compliment. Master data switches 312 and 314 may be implemented by, for example, n-channel complimentary metal oxide (CMOS) transistors although they may well be implemented by other types of transistor technologies. The combination of local data lines 308/310 and master data lines 316/318 carries the result ascertained by array sense amplifier 306 outside of the array area. As shown in FIG. 3, master data lines 316 and 318 are input into a master sense amplifier 320, which compares the potentials on master data lines 316 and 318, to output data on a R/W data line 322 to be furnished to the off-chip driver.
The provision of master data switches 312 and 314 is advantageous since multiple pairs of local data lines are typically coupled to any given pair of master data line. By appropriately manipulating the master data switches coupled to a given pair of master data lines, it is possible then to select the appropriate pair of local data lines for coupling to the pair of master data lines while deselecting (i.e., decoupling) the other pairs of local data lines from that pair of master data lines. In this manner, the capacitance associated with the conductive path between the array sense amplifier (e.g., array sense amplifier 306) and the master sense amplifier (e.g., master sense amplifier 320) is reduced since the inactive pairs of local data lines are not selected and are thus decoupled from the pair of master data lines that forms part of the conductive path.
It should be appreciated many pairs of local data lines, master data lines, and master data switches may be required in a given DRAM circuit. As such, the circuitry of FIG. 3 needs to be accommodated and laid out such that minimal additional space is required on the integrated circuit. In particular, it remains a challenge to lay out the local data lines, the master data switches, the master data lines, and the connections between these components such that both layout complexity and space usage is reduced.